Objectives

The end of the roadmap for scaling down CMOS technology has led to unsustainable growth of power consumption (e.g. 13 MW in Summit [1]) in data centres and high-performance computers (HPC). This has resulted in renewed interest in cryogenic computing schemes that offer extreme power efficiency, even taking the cooling power into account [2]. Furthermore, several companies and public consortia have recently invested heavily in the promising concept of quantum computation using superconducting circuits [3].

However, an important bottleneck for scaling up any cryogenic computing technology is the data transfer between the cryogenic electronics and the conventional information processing equipment required at room temperature. With a seamless high-bandwidth data link, the emerging technologies could leverage the vast transistor count of CMOS, rather than compete against it. In this vision, the cryogenic coprocessors would play a role similar to today’s GPUs, which assist CPUs in tasks like matrix multiplication that are an integral part of modern HPC, including machine learning.

CMOS itself can also be used in cryogenic environments, allowing lower operating voltages and thus lower power consumption [4,5], but more dramatic gains in energy efficiency are possible using single flux quantum (SFQ) technology [2]. The latter, and its variants such as energy-efficient SFQ (eSFQ), represent bits as short (~ 1 ps) pulses produced by switching processes in superconducting tunnel junctions called Josephson junctions. The typical energy of these pulses is only 0.2 aJ and they can be processed at speeds exceeding 100 GHz [6].

Quantum computing (QC) is still in its infancy, but there the most prominent approach is also based on superconducting Josephson junction technology. Here, the need for a high-bandwidth data bus arises from the large number of control and readout operations required to implement quantum error correction. Although cutting-edge realisations still rely on radio-frequency (RF) cables for the control and readout of the quantum bits (qubits), this approach is not sustainable because the heat load from these coaxial cables is already near the limits of state-of-the-art cryogenic technology. In the long term, the number of qubits will grow dramatically (≈106 qubits), and thus entirely new concepts for transmitting the control and readout signals will be required. Integrating low-level CMOS [4,5] or SFQ [7] components directly in the cryogenic environment partially alleviates this problem, but the complex classical processing associated with surface code based error correction [8] is still likely to require the processing power and memory capacity of conventional CMOS technology. A rough estimate for the data capacity need is 100 Mbit/s per qubit, corresponding to communicating four bits of information per qubit every 40 ns. Therefore, as in the case of classical supercomputers, the data bus must be densely integrated and consume little power in order to be scalable to large future systems. To address this data transfer bottleneck, aCryComm aims to develop novel electro-optic technologies for addressing superconducting computing platforms with record-breaking data rates and low dissipation. We will address the technological compatibility of superconducting digital logic operated at or near liquid helium temperature (T = 4.2 K), typically used for classical superconducting computing, and at < 100 mK, typically used for superconducting quantum computing (see figure above). For the two scenarios, the primary objective is to construct two types of laboratory-scale demonstrators:

  1. Demonstrate ultra-fast low-dissipation information transfer from room temperature to superconducting digital circuit at T = 4.2 K and back to the room temperature by means of an optical data bus.
  2. Demonstrate fast ultra-low-dissipation information flow from room temperature to a superconducting digital circuit at T = 20 mK and back to room temperature by means of an optical data bus.

 

As a further proof of the relevance of the topic, we note that a recent IARPA initiative (SuperCables [9]) identified optical data buses as a key technology for scaling up superconducting classical computing (i.e. in the 4 K scenario). In particular, the call stressed the lack of viable solutions to the electrical-to-optical (EO) cryogenic interfaces of Target 1, due to the low driving energy and voltage provided by SFQ circuits. It must be stressed that resorting to SFQs is a double-edged sword: on one hand, it allows ultra-low power computation and very high speed but, on the other hand, SFQ pulses provide very little energy to generate a modulated optical signal. The concurrence of high speed and low power consumption, imposes a strict upper boundary to the available energy per bit [10], which lays far beyond the state of the art (SoA) of electro-optic modulators (≈ fJ/bit). Even more challenging are the cryogenic interfaces for quantum computers (Target 2), due to stricter energy dissipation constraints, which require the development of single photon detectors with speed well beyond the SoA or, from a complementary point of view, of cryogenic ultra-high-speed detectors with very high quantum efficiency. For both classical and quantum computing, the key figures of merit that determine scalability of the OE and EO interfaces to very large systems are the power consumption per bit and the bandwidth per occupied physical area (footprint). We provide these numerical targets in the table below. The targets for 4 K operation are in line with the objectives listed in the recent IARPA SuperCables initiative [9].

Objectives - table

References

[1] Summit. Oak Ridge Leadership Computing Facility

[2] Holmes, D. S., Ripple, A. L. & Manheimer, M. A. Energy-Efficient Superconducting Computing—Power Budgets and Requirements. IEEE Trans. Appl. Supercond. 23, 1701610–1701610 (2013).

[3] Mohseni, M. et al. Commercialize quantum technologies in five years. Nat. News 543, 171 (2017).

[4] Patra, B. et al. Cryo-CMOS Circuits and Systems for Quantum Computing Applications. IEEE J. Solid-State Circuits 53, 309–321 (2018).

[5] Bardin, J. C. et al. A 28nm Bulk-CMOS 4-to-8GHz <2mW Cryogenic Pulse Modulator for Scalable Quantum Computing. ArXiv190210864 Quant-Ph (2019).

[6] Likharev, K. K. & Semenov, V. K. RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems. Appl. Supercond. IEEE Trans. On 1, 3–28 (1991).

[7] McDermott, R. et al. Quantum–classical interface based on single flux quantum digital logic. Quantum Sci. Technol. 3, 024004 (2018).

[8] Fowler, A. G., Whiteside, A. C. & Hollenberg, L. C. L. Towards Practical Classical Processing for the Surface Code. Phys. Rev. Lett. 108, (2012).

[9] IARPA project: SuperCables.

[10] Sorger, V. J. Plasmon Modulators. Nat. Nanotechnol. 10, 14 (2015).